In semiconductor product logic chips, such as ASIC chips, a high level of testability is required in order to eliminate all defective parts. A test coverage of more than 99.9% is usually expected with advanced semiconductor technologies. The test coverage is function of the predicted yield and the targeted Shipped Product Quality Level (SPQL) at system level. Circuits such as tie-up and/or tie-down circuits are often used for functionality purposes in combination with combinational logic books to form complex logic networks. As a matter of fact, a short to the VDD power supply would be equivalent to a tie-up function (which generates a logic "1"), and a short to the ground (GND) power supply would be equivalent to a tie-down function (which generates a logic "0"). Admittedly, these tie-up/tie-down circuits are testability killers in some respect with the current "stuck-at" fault model because they prevent fault activation/sensitization or fault extraction. For example, if the input and/or the output of a logic book is continuously forced to a determined logic value, it cannot be completely tested. Unfortunately, the stuck-at fault model does not always correlate with the actual hardware faults, especially when the CMOS technology is employed. However, the technical community agrees to consider this model the only acceptable one to calculate efficiently the testability of the high density ASIC chips designed to date. The testability-is calculated over the "flat" structure of the complete design built from elementary logic books such as AND, NAND, OR, NOR, . . . , etc. To each input and output of these elementary books is assigned two data: one "stuck-at-1" and one "stuck-at-0". The stuck-at-1 indicates the wiring net which is connected to the input (or output) is blocked (stuck) to the logic level "1", while the stuck-at-0 indicates the wiring net is blocked to the logic level "0".
As usually known for those ordinary skilled in the art, before a product chip is shipped in a system to the customer, it is extensively tested in the manufacturing environment, during the so-called final test step. A. standard product chip has thus two basic operating modes: the SYSTEM mode according to which the product chip is in normal operation in a system at customer location and the TEST mode in the manufacturing environment.
In the TEST mode, when a test configuration can sensitize one (or several) stuck-at-fault (s) and the result-can be observed for subsequent extraction by the tester on one output of the DUT (device under test), this fault is then declared detectable. Accordingly, it is removed from the list of untested faults and thus contributes to increase the score of the testability. The testability being the number of tested stuck-at faults over the total number of stuck-at faults. It is easy to realize that because the output of a tie-up (tie-down) circuit is tied to the VDD (GND) power supply, it cannot be switched to the opposite logic level to detect a-stuck-at-1 (stuck-at-0). Finally, when all the tie-up/tie-down circuits and related logic books of the said complex logic networks are interconnected, the total testability of the said complex logic networks is thus decreased. This will be explained by reference to FIG. 1, which shows a piece of a conventional complex logic network 10 and a tie-up circuit 11 associated therewith.
Now turning to FIG. 1, there are shown a logic network 10 including both combinational and sequential logic books and a tie-up circuit 11. The output (A) of said tie-up circuit 11 is connected to the first input of a logic elementary book 12, e.g. an OR-INVERTER (OI) gate, whose second input is connected to the output of a latch 13. The output (C) of book 12 is connected to one input (E) of an OR (O) gate 14 and to one input (F) of an OR-INVERTER (OI) gate 15. The test generation system creates for each input/output of each book, e.g. OI 12, a pair of stuck-at-faults (0 and 1). During the normal test operation (TEST mode) certain stuck-at faults are detected, while others, for instance those referenced by-arrows 16 to 19 in path ABCDE, cannot be sensitized and thus remain as undetected stuck-at faults.
More generally, all the logic paths controlled by either a tie-up or a tie-down circuit see their testability affected. As of today, there are two conventional approaches to implement the TEST mode. The first one is to avoid this testability impact by reducing the number of books controlled by the said tie-up/tie-down circuits. The second one consists to ignore all stuck-at faults present on the logic books affected by them.
According to the first approach, as we have said before, any stuck-at fault which can be sensitized and observed will increase the testability score. Here, as apparent from FIG. 1, for the above mentioned path ABCDE, only 50% of the stuck-at faults which are directly under the tie-up circuit 11 control are untestable due to the impossibility to generate an opposite state thereto. Consequently, one way to reduce the testability impact is therefore to reduce the number of books e.g. books 12, 14 and 15, directly controlled by the tie-up circuit 11. Same reasoning applies to tie-down circuits.
The test engineer with his fault extraction methods may point out a low testability of the functional logic network as originally designed by the logic designer, because the presence of untestable faults resulting from tie-up/tie-down circuits. As a result, the logic designer would have to spend again a lot of additional time to identify the books controlled by such tie-up/tie-down circuits and modify its original design. This is even more true in case of previous use of logic synthesis, which is very likely with present large chips. High logic and test design skills are thus required to manually change the original design. At this point of the design cycle, such changes for necessitate a manual and complex interactive process between the logic designer and the test engineer. This is a lengthy process prone to errors. In addition, the logic overhead that needs to be added to attain reduction in the number of tie-up/tie-down circuits may be substantial, then resulting in a loss in terms of-circuit density. Finally, the overall design and validation time may be quite significantly increased. It could be very difficult to find the untested faults that have been generated because of the tie-up/tie-down circuits, as current stuck-at fault detection algorithms may be limited.
According to the second approach, a new technique has been recently introduced to classify all the untested stuck-at faults due to tie-up/tie-down circuits, as IGNORED faults. These IGNORED faults do not participate to the final testability computation. This is justified by the fact that these untested stuck-at faults tend to duplicate the tie-up or tie-down function. This point is illustrated in FIG. 1 by stuck-at-1 faults 16 and 17 which duplicate the function of tie-up circuit 11.
Now the problem arises of determining whether an hardware built-in defect which creates a fault that generates a correct function in an ASIC chip when used in SYSTEM mode, must be considered as an actual fault or a fault that can be ignored. Let us assume for instance that stuck-at fault 17 is created by an hardware built-in defect (e.g. an unexpected short between interconnection line AB and the VDD supply voltage), this hardware defect duplicates the tie-up function assured by tie-up circuit 11. Should this untested stuck-at-1 fault 17 which modelizes this hardware built-in defect, be considered as an actual fault or not, and in the latter case can be thus ignored.
When the number of such IGNORED faults stays low, their testability impact is negligible and this approach seems acceptable. However, as soon as the design uses a large number of tie-up/tie-down functions, the testability computation would be in error, and the SPQL highly degraded. More generally, according to the SPQL theory, for any test sequence, product defects of the physical type (therefore including said hardware built-in defects) are divided into two categories, which in turn, define two areas: the area of detected product defects and the area of undetected product defects. The theory behind the SPQL calculation indicates that the quality of the area of undetectable product defects depends on the ratio between the detectable and undetectable product defects. The more the area of detected product defects (testable) is important, the less the area of undetected product defect non-testable will contain faults. The consequence is that one must increase the number of-detectable defects, irrespective the said product physical defects create or not functionnality faults. Finally, the overall quality of the product is improved if the stuck-at-faults controlled by the tie-up/tie-down functions are tested.
On the other hand, besides this SPQL theory, one must also take into account the consequence on the reliability of the product containing IGNORED faults. It is very likely that these physical defects represented (modellized) by these IGNORED faults, will evolve with time. For instance, a short at time of shipping the product to the customer, may become an open sometimes in its life thus creating a real failure, that can modify the functional behavior of the logic network normally operating in SYSTEM mode.
In summary, the first approach has some inconveniences because it is really a complex process. The testability could not directly reach the high expected level e.g. 99.9 % minimum, that is sought, and in turn, the SPQL will be degraded. The logic designer must add several circuits only used to improve testability (in this case, additional overhead may be quite important) or modify other circuits in the design as explained above. Or instead, according to the second approach, because the stuck-at faults are ignored, the so-called IGNORED faults, the SPQL is likewise degraded.
An illustration of these still existing difficulties are set forth in a recent article: "Designers need new ways of handling faults to build testability into today's ICs" published in Electronics World news 28 Jan. 1992 pp 29-32. In essence, this article concludes that functional testing cannot lead to a satisfactory solution of tie-up/tie-down circuit testability pursuant to the above mentioned second approach. As a result, there has been a constant need for a long time to implement a satisfactory solution from a SPQL point of view.